The present invention relates to a semiconductor memory device and methods of manufacturing same.
A one transistor-one capacitor memory cell including a single switching transistor and a single capacitor and used as a memory cell for a high-density DRAM is widely used because it includes few components and has a cell area which is easily miniaturized.
In particular, the miniaturization of the cell area is effected by forming a trench in the semiconductor substrate, forming a switching transistor in an island area surrounded by the trench, and using the trench side as a capacitor, as disclosed in FIGS. 1 and 2 which show a conventional semiconductor memory device as illustrated in a publication by Shigeru Nakajima et al, "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", IEDM TECHNICAL DIGEST, 1984, pp. 240-243.)
FIG. 1 is a schematic plan view of a conventional memory cell. FIG. 2 is a schematic cross section view of the conventional memory cell taken along the line I-I' of FIG. 1. For convenience of explanation, the same components are given the same reference numeral in FIGS. 1 and 2. Reference numeral 101 denotes a p-type semiconductor substrate; 102, an n.sup.+ -type impurity layer forming the drain of a switching transistor; 103, an n.sup.+ -type impurity layer forming the source of the switching transistor; 104, a gate insulating film; 105, a word line; 106, a bit line; 107, a bit line comprising a contact window between the bit line and drain; 110, a trench formed around the switching transistor; 111, an insulating film formed inside the trench 110; 112, a storage electrode of poly-silicon which electrically connects the source 103 and a window 113; 114, a capacitor insulating film formed on the storage electrode 112; 115, a plate electrode forming a memory cell capacitor together with the storage electrode 112 and capacitor insulating film 114; 116, an isolated oxidation film obtained by oxidizing an upper portion of the poly-silicon forming the plate electrode 115 in the trench; and 117, an inter-layer insulating film.
In the arrangement in which the periphery of the island in which the switching transistor is formed is used as both the capacitor and isolated insulating area of the memory cell, however, there would occur a leak current in the switching transistor due to the parasitic MOSFET effect and a leak current in the cell capacitor due to the gate controlled diode effect in the trench sidewall of the cell capacitor.
As shown in FIG. 3, since the poly-silicon composing the storage electrode 112 is buried around the switching transistor, a parasitic MOSFET transistor is formed in the trench sidewall along the channel of the switching transistor. The storage electrode 112 acts effectively as a gate electrode in the trench sidewall to control the flow of an electric current through the source-drain of the switching transistor, separately from a regular word line. Therefore, when the voltage level of the storage electrode 112 changes to high (for example, to Vcc), a leak current is produced flowing through the source-drain of the switching transistor.
A gate controlled diode structure is formed on the trench sidewall out of the storage electrode 112, the sidewall insulating film 111, and the source 103 of the switching transistor. Therefore, the voltage level of the storage electrode changes from 0 V to Vcc, a depletion layer extends to the trench sidewall due to the gate controlled diode effect, and a leak current is produced due to a defect in the oxide film-Si interface on the trench sidewall.
In summary, the problems to be solved are as follows:
(1) To prevent the generation of a leak current due to parasitic MOS transistor effect on the sidewall of a trench formed in the isolation region along the channel in an isolation-merged memory cell which uses the trenched isolation region around the switching transistor as a memory cell capacitor; PA1 (2) To prevent the generation of a gate controlled diode leak current between the source of the switching transistor and the substrate on the trench sidewall. PA1 (1) to prevent the generation of a leak current due to parasitic MOS transistor effect on the trench sidewall along the channel in the switching transistor; and PA1 (2) to prevent the generation of a gate controlled diode leak current between the source of the switching transistor and the substrate on the trench sidewall.